Altera 10-Gbps Ethernet MAC MegaCore Function - Manual (Page 132)

Chapter 9: Interface Signals 9–13
February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide
9.0.7. Avalon-ST Status and Pause Interface Signals
Table 9–8 describes the Avalon-ST status signals.
1
Use the Avalon-ST status interface to obtain information and error status on receive
frames only when the option to remove CRC and/or padding is disabled and no
overflow occurs. When CRC and/or padding removal is enabled or when an
overflow occurs (avalon_st_rx_ready is deasserted), obtain the same information
using the statistics counters.
Table 9–8. Avalon-ST Status Interface Signals (Part 1 of 5)
Signal Direction Width Description
avalon_st_rxstatus_valid Output 1
When asserted, this signal indicates that
avalon_st_rxstatus_data[]
contains valid
information about the receive frame.
The IP core asserts this signal in the same clock cycle it
receives the end of packet (avalon_st_rx_endofpacket
is asserted).
avalon_st_rxstatus_data[] Output 40
Contains information about the receive frame:
■ Bits 0 to 15: Payload length.
■ Bits 16 to 31: Packet length.
■ Bit 32: When set to 1, indicates a stacked VLAN frame.
■ Bit 33: When set to 1, indicates a VLAN frame.
■ Bit 34: When set to 1, indicates a control frame.
■ Bit 35: When set to 1, indicates a pause frame.
■ Bit 36: When set to 1, indicates a broadcast frame.
■ Bit 37: When set to 1, indicates a multicast frame.
■ Bit 38: When set to 1, indicates a unicast frame.
■ Bit 39: When set to 1, indicates a PFC frame.
The IP core presents the valid information on this bus in
the same clock cycle it asserts
avalon_st_rxstatus_valid
. The information on this
data bus is invalid when an overflow occurs or when CRC
and/or padding removal is enabled.