Altera 10-Gbps Ethernet MAC MegaCore Function User Manual
Page 105

Chapter 8: Registers
8–11
MAC Registers
February 2014
Altera Corporation
10-Gbps Ethernet MAC MegaCore Function User Guide
0x0C01
Reserved
—
—
Reserved for future use.
0x1C01
0x0C02
rx_stats_framesOK
RO
0x0
■
Bit 0—The number of frames that are
successfully received or transmitted,
including control frames.
■
36-bit width register:
■
0x0C02 and 0x1C02 = bits [31:0]
■
0x0C03 and 0x1C03 = bits [35:32]
0x0C03
0x1C02
tx_stats_framesOK
0x1C03
0x0C04
rx_stats_framesErr
(2)
RO
0x0
■
Bit 0—The number of errored frames that
are received or transmitted, including
control frames.
■
36-bit width register:
■
0x0C04 and 0x1C04 = bits [31:0]
■
0x0C05and 0x1C05 = bits [35:32]
0x0C05
0x1C04
tx_stats_framesErr
(2)
0x1C05
0x0C06
rx_stats_framesCRCErr
RO
0x0
■
Bit 0—The number of receive or transmit
frames with only CRC error.
■
36-bit width register:
■
0x0C06 and 0x1C06 = bits [31:0]
■
0x0C07 and 0x1C07 = bits [35:32]
0x0C07
0x1C06
tx_stats_framesCRCErr
0x1C07
0x0C08
rx_stats_octetsOK
RO
0x0
■
Bit 0—The number of data and padding
octets that are successfully received or
transmitted, including control frames.
0x0C09
0x1C08
tx_stats_octetsOK
0x1C09
0x0C0A
rx_stats_pauseMACCtrl Frames
RO
0x0
■
Bit 0—The number of valid pause frames
received or transmitted.
■
36-bit width register:
■
0x0C0A and 0x0C0B = bits [31:0]
■
0x1C0A and 0x1C0B = bits [35:32]
0x0C0B
0x1C0A
tx_stats_pauseMACCtrl Frames
0x1C0B
0x0C0C
rx_stats_ifErrors
RO
0x0
■
Bit 0—The number of errored and invalid
frames received or transmitted.
■
36-bit width register:
■
0x0C0C and 0x0C0D = bits [31:0]
■
0x1C0C and 0x1C0D = bits [35:32]
0x0C0D
0x1C0C
tx_stats_ifErrors
0x1C0D
0x0C0E
rx_stats_unicast FramesOK
RO
0x0
■
Bit 0—The number of good unicast frames
that are successfully received or
transmitted, excluding control frames.
■
36-bit width register:
■
0x0C0E and 0x0C0F = bits [31:0]
■
0x1C0E and 0x1C0F = bits [35:32]
0x0C0F
0x1C0E
tx_stats_unicast FramesOK
0x1C0F
Table 8–2. MAC Registers (Part 10 of 15)
Word
Offset
Register Name
Access
Reset
Value
Description