Altera 10-Gbps Ethernet MAC MegaCore Function - Manual (Page 113)

Chapter 8: Registers 8–19
Register Initialization
February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide
8.2.1. Configuring PMA Analog and Digital Delay
You need to configure the PMA analog and digital delay to adjust the registers. The
TX and RX paths are configured individually.
Table 8–6 lists the analog delay for the different MAC variants.
Table 8–7 lists the digital delay for the different MAC variants.
1
1 UI for 10G is 97 ps, and 1 UI for 1G/100M/10M is 800 ps.
8.3. Register Initialization
Altera offers the following options for the 10GbE solution with the 10G MAC IP core:
■ 10GbE MAC with single data rate (SDR) XGMII
■ 10GbE MAC with double data rate (DDR) XGMII
■ 10GbE MAC with XAUI PHY IP
■ 10GbE MAC with 10GBASE-R PHY IP
0x0113
(10 Gbps mode)/
0x011B
(1 Gbps, 10 Mbps,
and 100 Mbps
mode)
rx_adjust_ns RW
Static timing adjustment in nanoseconds for
outbound timestamps on the receive datapath.
■ Bits 0 to 15: Timing adjustment in nanoseconds.
■ Bits 16 to 23: Not used.
0x0
0x1113
(10 Gbps mode)/
0x111B
(1 Gbps, 10 Mbps,
and 100 Mbps
mode)
tx_adjust_ns RW
Static timing adjustment in nanoseconds for
outbound timestamps on the transmit datapath.
■ Bits 0 to 15: Timing adjustment in nanoseconds.
■ Bits 16 to 23: Not used.
0x0
Table 8–5. MAC Registers for 1GbE MAC with IEEE 1588v2 Feature (Part 2 of 2)
Word Offset Name R/W Description
HW
Reset
Table 8–6. Analog Delay
Device Family TX (ns) RX (ns) MAC Variant
Arria V –1.1 1.75 All
Stratix V –1.1 1.75 All
Table 8–7. Digital Delay
Device Family PMA Mode (bit) TX (UI) RX (UI) MAC Variant
Arria V GZ and Stratix V
40 123 87 10GbE or 10G of 10M-10GbE
32 99 84 10GbE
10 53 26 1G/100M/10M of 10M-10GbE
Arria V GX, Arria V GT, and Arria V SoC
64 66 165 10GbE or 10G of 10M-10GbE
10 42 44 1G/100M/10M of 10M-10GbE