Altera 10-Gbps Ethernet MAC MegaCore Function - Manual (Page 52)

Chapter 5: 1G/10GbE MAC Design Example 5–7
1G/10GbE Testbench
February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide
5.5.2. 1G/10GbE Testbench Components
The testbenches comprise the following modules:
■ Device under test (DUT)—the design example.
■ Avalon driver—uses Avalon-ST master bus functional models (BFMs) to exercise
the transmit and receive paths. The driver also uses the Avalon-MM master BFM
to access the Avalon-MM interfaces of the design example components.
■ Packet monitors—monitors the transmit and receive datapaths, and displays the
frames in the simulator console.
5.5.3. 1G/10GbE Testbench Files
The <ip library>/ethernet/altera_eth_10g_design_example/testbench directory
contains the testbench files.
Table 5–4 describes the files that implement the 1G/10GbE testbench.
Figure 5–4. 1G/10GbE Testbench Block Diagram
Loopback
on Serial
Testbench
Avalon-MM
Ordinary Clock
Transparent Clock
Avalon-MM
Control
Register
Avalon-ST
Transmit
Frame
Generator
Avalon-ST
Receive
Frame
Monitor
Ethernet
Packet
Monitor
Ethernet
Packet
Monitor
DUT
avalon_bfm_wrapper.sv
Avalon Driver
Channel-0
Channel-1
Avalon-ST
Avalon-ST
Table 5–4. 1G/10GbE Testbench Files
File Name Description
avalon_bfm_wrapper.sv
A wrapper for the Avalon BFMs that the avalon_driver.sv file
uses.
avalon_driver.sv
A SystemVerilog HDL driver that utilizes the BFMs to exercise
the transmit and receive path, and access the Avalon-MM
interface.