10gbe with ieee 1588v2 design example files, Creating a new 10gbe with ieee 1588v2 design – Altera 10-Gbps Ethernet MAC MegaCore Function User Manual
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Chapter 4: 10GbE MAC with IEEE1588v2 Design Example
10GbE with IEEE 1588v2 Design Example Files
10-Gbps Ethernet MAC MegaCore Function User Guide
February 2014
Altera Corporation
4.3. 10GbE with IEEE 1588v2 Design Example Files
shows the directory structure for the 10GbE with IEEE 1588v2 design
examples and testbenches.
lists the files in the
..\altera_eth_10g_mac_base_r_1588
directory.
4.4. Creating a New 10GbE with IEEE 1588v2 Design
You can use the Quartus II software to create a new 10GbE with IEEE 1588v2 design.
Altera provides a Qsys design example file that you can customize to facilitate the
development of your 10GbE with IEEE 1588v2 design.
To create the design, perform the following steps:
1. Launch the Quartus II software and open the
altera_eth_10g_mac_base_r_1588_top.v
file from the project directory.
2. Launch Qsys from the Tools menu and open the
altera_eth_10g_mac_base_r_1588.qsys
file. By default, the design example targets
the Stratix V device family. To change the target device family, click on the Project
Settings
tab and select the desired device from the Device family list.
3. Turn off the additional module under the Use column if your design does not
require it. This action disconnects the module from the 10GbE with IEEE 1588v2
system.
4. Double-click on eth_10g_design_example_0 to launch the parameter editor.
5. Specify the required parameters in the parameter editor.
6. Click Finish.
7. On the Generation tab, select either a Verilog HDL or VHDL simulation model
and make sure that the Create HDL design files for synthesis option is turned on.
Figure 4–2. 10GbE with IEEE 1588v2 Design Example Folders
Table 4–2. 10GbE with IEEE 1588v2 Design Example Files
File Name
Description
altera_eth_10g_mac_base_r_1588_top.v
The top-level entity file of the design example for
verification in hardware.
altera_eth_10g_mac_base_r_1588_top.sdc
The Quartus II SDC constraint file for use with
the TimeQuest timing analyzer.
altera_eth_10g_mac_base_r_1588.qsys
A Qsys file for the 10GbE MAC and 10GBASE-R
PHY design example with IEEE 1588v2 option
enabled.
altera_eth_10g_mac_base_r_1588
testbench