Altera 10-Gbps Ethernet MAC MegaCore Function - Manual (Page 114)

8–20 Chapter 8: Registers
Register Initialization
10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation
f To learn more about the 10G MAC with SDR XGMII to DDR XGMII conversion, refer
to
“SDR XGMII to DDR XGMII Conversion” on page 10–1 .
The 10G MAC is configured in promiscuous (transparent) mode at default or after a
hard reset. In promiscuous mode, the 10GbE MAC does not perform any MAC
address filtering and it is capable of transmitting and receiving all types of Ethernet
frames.
Register initialization for the 10GbE MAC design example is mainly performed in the
following configurations:
■ External PHY Initialization Using MDIO (Optional)
■ PHY Configuration Register Initialization
■ Miscellaneous Configuration Register Initialization
■ MAC Configuration Register Initialization
f For more information about the 10GbE MAC design example, refer to the “Design
Examples and Testbench” chapter.
To initialize the registers for the 10GbE MAC configuration, it is important for you to
understand the usage of the addressing mode. This configuration uses the following
addressing modes:
■ 10GbE MAC MAC IP Core—dword addressing
■ 10GbE design example—byte addressing
You can easily convert between dword and byte addressing by removing or adding
two least significant bits (LSB) in the address. For example, if dword = 0x341, you can
add two LSB bits to the byte address conversion to get byte address = 0xD04.
Use the following recommended register initialization sequences for 10GbE MAC
design example:
1. External PHY initialization using MDIO
This is only applicable when you require external PHY transceiver configuration.
//Assume:
//External PHY Address (Hardwired) (MDIO_PRTAD): 0x01
//External PHY Device Type (MDIO_DEVAD): 0x01
//External PHY Control Register address (MDIO_REGAD): 0x0000
//MDIO Base Address: 0x00010000
//MDIO Register Byte offset: 0x84 Byte Address, 0x00010084 = 0x00000104
//Read/Write to External PHY Control Register define in MDIO_REGAD
//MDIO Base Address: 0x00010000
//MDIO Register Byte offset: 0x80
Read/write to Byte Address, 0x00010080 = Read/write to PHY Control
Register (Device Address = 0x01, Register Address = 0x0000)