Altera 10-Gbps Ethernet MAC MegaCore Function - Manual (Page 148)

Chapter 9: Interface Signals 9–29
February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide
Figure 9–11 shows the TX timestamp signals for the second type of egress correction
field update, where the 64 bit ingress timestamp has been pre-subtracted from the
correction field at the ingress port. At the egress port, the 64 bit egress timestamp is
added into the correction field and the correct residence time is updated in the
correction field. This is the example of PTP frame encapsulated over UPD/IPV6.
Figure 9–11. Type 2 Egress Correction Field Update
Type 2 Egress Correction Field Update, 64b, IPV6
2-step Timestamp Request,Input
tx_egress_timestamp_request_valid
tx_egress_timestamp_request_data[N:0]
2-step Timestamp Return,Output
tx_egress_timestamp_96b_valid
tx_egress_timestamp_96b_fingerprint[N:0]
tx_egress_timestamp_96b_data[95:0]
tx_egress_timestamp_64b_valid
tx_egress_timestamp_64b_fingerprint[N:0]
tx_egress_timestamp_64b_data[63:0]
1-step Timestamp Insert,Input
tx_etstamp_ins_ctrl_timestamp_insert
tx_etstamp_ins_ctrl_timestamp_format
1-step Residence Time Update,Input
tx_etstamp_ins_ctrl_residence_time_update
tx_etstamp_ins_ctrl_ingress_timestamp_96b[95:0]
tx_etstamp_ins_ctrl_ingress_timestamp_64b[63:0]
tx_etstamp_ins_ctrl_residence_time_calc_format
1-step IPv4 and IPv6 Checksum,Input
tx_etstamp_ins_ctrl_checksum_zero
tx_etstamp_ins_ctrl_checksum_correct
1-step Location Offset,Input
tx_etstamp_ins_ctrl_offset_timestamp[15:0]
Offset 1 tx_etstamp_ins_ctrl_offset_correction_field[15:0]
Offset 2
tx_etstamp_ins_ctrl_offset_checksum_field[15:0]
tx_etstamp_ins_ctrl_offset_checksum_correction[15:0]
64’b0
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