Altera 10-Gbps Ethernet MAC MegaCore Function User Manual
Page 69
7–2
Chapter 7: Functional Description
Architecture
10-Gbps Ethernet MAC MegaCore Function User Guide
February 2014
Altera Corporation
Figure 7–1
show the block diagrams of the 10GbE MAC,
1G/10GbE MAC, and 10M-10GbE MAC variants of the MAC IP core.
Figure 7–1. 10GbE MAC IP Core Block Diagram
Figure 7–2. 1G/10GbE MAC IP Core Block Diagram
Avalon-MM
Bridge
10GbE MAC
XGMII
Transmit
Interface
64-bit
Avalon-ST
Receive Interface
Avalon-MM
Configuration
64-bit
Avalon-ST
Transmit Interface
XGMII
Receive
Interface
Link
Fault
Flow
Control
MAC Tx
MAC Rx
64
64
32
72
72
Avalon-MM
Bridge
1G/10GbE MAC
64-bit
Avalon-ST
Receive Interface
Avalon-MM
Configuration
64-bit
Avalon-ST
Transmit Interface
Link
Fault
Flow
Control
MAC Tx
MAC Rx
64
64
32
XGMII
Transmit
Interface
72
GMII
Transmit
Interface
8
GMII
Receive
Interface
8
XGMII
Receive
Interface
72
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)