Altera 10-Gbps Ethernet MAC MegaCore Function - Manual (Page 104)

8–10 Chapter 8: Registers
MAC Registers
10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation
0x1201 tx_addrins_macaddr0 RW 0x0 6-byte MAC address. You must map the
address to the registers in the following
manner:
■ tx_addrins_macaddr0 = Last four bytes
of the address
■ tx_addrins_macaddr1 [0:15] = First two
bytes of the address.
Bits 16 to 31 are reserved.
Example:
If the primary MAC address is 00-1C-23-17-
4A-CB, set tx_addrins_macaddr0 to
0x23174ACB and tx_addrins_macaddr1 to
0x0000001C.
The IP core writes this address to the source
address field of transmit frames when address
insertion on transmit is enabled (refer to
description of tx_addrins_control).
0x1202 tx_addrins_macaddr1 RW 0x0
0x1203 –
0x17FF
Reserved — — Reserved for future use.
TX Frame Decoder (0x1800:0x1BFF)
0x1800 Reserved — — Reserved for future use.
0x1801 tx_frame_maxlength RW 1518
■ Bits 0 to 15 specifies the maximum
allowable frame length for the statistic
counter. The MAC asserts the
avalon_st_txstatus_error[1]
signal
when the length of the transmit frame
exceeds the value of this register and flags
it as oversized frame.
The value of this register does not affect the
allowable frame size that can be sent
through the Tx path.
■ Bits 16 to 31 are reserved.
0x1802 –
0x1BFF
Reserved — — Reserved for future use.
RX Statistics Counters (0x0C00:0x0FFF)—Collect statistics on the receive path. Prefixed with rx_. (1)
TX Statistics Counters (0x1C00:0x1FFF)—Collect statistics on the transmit path. Prefixed with tx_.
0x0C00 rx_stats_clr RWC 0x0
■ Bit 0—Set this register to 1 to clear all
statistics counters for the receive path.
■ Bits 1 to 31 are reserved.
0x1C00 tx_stats_clr RWC 0x0
■ Bit 0—Set this register to 1 to clear all
statistics counters for the transmit path.
■ Bits 1 to 31 are reserved.
Table 8–2. MAC Registers (Part 9 of 15)
Word
Offset
Register Name Access
Reset
Value
Description