Altera 10-Gbps Ethernet MAC MegaCore Function - Manual (Page 20)

3–2 Chapter 3: 10GbE MAC Design Examples
10GbE Design Example Components
10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation
3.2. 10GbE Design Example Components
You can use the 10GbE MAC IP core design example to simulate a complete 10GbE
design in an Altera FPGA. You can compile the design example using the simulation
files generated by the Quartus II software and program the targeted Altera device
after a successful compilation.
Figure 3–1 shows the block diagram of the 10GbE design examples.
Figure 3–1. 10GbE Design Example Block Diagram
Ethernet
Loopback
JTAG to Avalon Master
Bridge
Pipeline Bridge
10GbE MAC
XAUI
or
10GBASE-R
PHY
External
PHY
MDIO
64-bit Avalon-ST
64-bit Avalon-ST
32-bit
Avalon-MM
MDIO Signals
32-bit A
valon-MM
System Console
(for debugging)
XAUI / 10GBASE-R
72-bit SDR XGMII
72-bit SDR XGMII
Tx FIFO Buffer Rx FIFO Buffer
Client
Application
Altera FPGA
Design Example
Client Application
(Configuration, Status, and
Statistics)
Avalon-ST
Single-Clock / Dual-Clock
FIFO
Configuration and Debugging Tools
32
64 64
72 72
72 72
32
64 64