Altera 10-Gbps Ethernet MAC MegaCore Function - Manual (Page 100)

8–6 Chapter 8: Registers
MAC Registers
10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation
0x804 rx_frame_spaddr0_0 RW 0x0 You can specify up to four 6-byte
supplementary addresses:
■ rx_framedecoder_spaddr0_0/1
■ rx_framedecoder_spaddr1_0/1
■ rx_framedecoder_spaddr2_0/1
■ rx_framedecoder_spaddr3_0/1
You must map the supplementary addresses
to the respective registers in the same manner
as the primary MAC address. Refer to the
description of rx_frame_addr0 and
rx_frame_addr1
.
The IP core uses the supplementary addresses
to filter unicast frames when the following
conditions are set:
■ The use of the supplementary addresses
are enabled using the respective bits in the
rx_frame_control
register (refer to
“Rx_frame_control Register” on
page 8–16
).
■ The en_allucast bit of the
rx_frame_control
register is set to 0.
0x805 rx_frame_spaddr0_1 (1) RW 0x0
0x806 rx_frame_spaddr1_0 RW 0x0
0x807 rx_frame_spaddr1_1 (1) RW 0x0
0x808 rx_frame_spaddr2_0 RW 0x0
0x809 rx_frame_spaddr2_1 (1) RW 0x0
0x80A rx_frame_spaddr3_0 RW 0x0
0x80B rx_frame_spaddr3_1 (1) RW 0x0
0x818 rx_pfc_control RW 0x1
PFC enable for the priority queues on the
receive datapath.
Refer to “Rx_pfc_control Register” on
page 8–17 for the bit description.
0x819 –
0xBFF
Reserved — — Reserved for future use.
TX Packet Transfer (0x1000:0x103F)
0x1000 tx_transfer_control RW 0x0
Backpressure enable.
■ Bit 0 configures transmit transfer control.
0—Enables transmit transfer datapath.
1—Disables transmit transfer datapath on
the Avalon-ST transmit interface. The IP
core deasserts the avalon_st_tx_ready
signal.
■ Bits 1 to 31 are reserved.
0x1001 tx_transfer_status RO 0x0
■ Bit 0 indicates if transmit transfer datapath
is enabled on the Avalon-ST transmit
interface.
0—Transmit transfer datapath is enabled.
1—Transmit transfer datapath is disabled.
■ Bits 1 to 31 are reserved.
0x1002 –
0x103F
Reserved — — Reserved for future use.
TX Pad Inserter (0x1040:0x107F)
Table 8–2. MAC Registers (Part 5 of 15)
Word
Offset
Register Name Access
Reset
Value
Description