Verifying the 10gbe design in hardware, Debugging – Altera 10-Gbps Ethernet MAC MegaCore Function User Manual

Page 35

Chapter 3: 10GbE MAC Design Examples

3–17

10GbE Design Example Compilation and Verification in Hardware

February 2014

Altera Corporation

10-Gbps Ethernet MAC MegaCore Function User Guide

3.7.2. Verifying the 10GbE Design in Hardware

After programming the targeted Altera device, follow these steps to verify your
design and collect the statistics:

1. Copy the csr_scripts directory to the design example directory.

2. Launch Qsys and access the System Console by clicking System Console on the

Tools menu.

3. Change the working directory to /csr_scripts.

4. Type the following command to configure the design example:

source config.tcl

5. Start frame transmission on your remote partner to exercise the datapaths.

6. Type the following command to read and view the statistics:

source show_stats.tcl

The config.tcl and show_stats.tcl scripts support only one USB-Blaster
connection.

3.7.3. Debugging

You can use the system console to perform the following tasks for debugging
purposes:

■

Reconfigure the design example components and retrieve the registers during
runtime by following these steps:

a. Create a new Tcl script.

b. Add the following commands:

source common.tcl

# establishes the connection

open

_jtag

# use rd32 to retrieve the register value
# base address = base address of the component
# offset = byte offset of the register
rd32 0

# use wr32 to configure the register
# base address = base address of the component
# offset = byte offset of the register
# value = value to be written to the register
wr32 0

# closes the connection

_jtag

Save and close the Tcl script and type the following command:

source