Altera 10-Gbps Ethernet MAC MegaCore Function - Manual (Page 168)

Appendix D: ToD Synchronizer D–3
February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide
Altera recommends that you use the following sampling clock frequencies:
■ 1G master and slave—(64/63)*125MHz
■ 10G master and slave—(64/63)*156.25MHz
■ 1G master and 10G slave—(16/63)*125MHz or (64/315)*156.25MHz
■ 10G master and 1G slave—(16/63)*125MHz or (64/315)*156.25MHz
Table D–2 shows the settings to achieve the recommended factors for Stratix V PLL.
D.3. ToD Synchronizer Parameter Settings
Table D–2 describes the ToD Synchronizer configuration parameters.
Table D–1. Settings to Achieve The Recommended Factors for Stratix V PLL
Settings 64/63 16/63 64/315
M-Counter 64 16 64
N-Counter 21 03 21
C-Counter 03 21 15
Table D–2. ToD Synchronizer Configuration Parameters
Name Value Description
TOD_MODE Between 0 and 1
Value that defines the time of day format that this block
is synchronizing.
The default value is 1.
1: 96-bits format (32 bits seconds, 48 bits nanosecond
and 16 bits fractional nanosecond)
0: 64-bits format (48 bits nanosecond and 16 bits
fractional nanoseconds).
SYNC_MODE Between 0 and 2
Value that defines types of synchronization.
The default value is 1.
0: Master clock frequency is 125MHz (1G) while slave
is 156.25MHz (10G).
1: Master clock frequency is 156.25MHz (10G) while
slave is 125MHz (1G).
2: Master and slave are same in the same frequency;
can be in different ppm or phase. When you select this
mode, specify the period of master and slave through
the PERIOD_NSEC and PERIOD_FNSEC parameters.