Altera 10-Gbps Ethernet MAC MegaCore Function - Manual (Page 108)

8–14 Chapter 8: Registers
MAC Registers
10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation
0x0C26
rx_stats_etherStats
Pkts128to255Octets
RO 0x0
■ Bit 0—The number of receive or transmit
frames between the length of 128 and 255
bytes, including the CRC field but excluding
the preamble and SFD bytes. This count
includes good, errored, and invalid frames.
■ 36-bit width register:
■ 0x0C26 and 0x0C27 = bits [31:0]
■ 0x1C26 and 0x1C27 = bits [35:32]
0x0C27
0x1C26
tx_stats_etherStats
Pkts128to255Octets 0x1C27
0x0C28
rx_stats_etherStats
Pkts256to511Octets
RO 0x0
■ Bit 0—The number of receive or transmit
frames between the length of 256 and 511
bytes, including the CRC field but excluding
the preamble and SFD bytes. This count
includes good, errored, and invalid frames.
■ 36-bit width register:
■ 0x0C28 and 0x0C29 = bits [31:0]
■ 0x1C28 and 0x1C29 = bits [35:32]
0x0C29
0x1C28
tx_stats_etherStats
Pkts256to511Octets 0x1C29
0x0C2A
rx_stats_etherStats
Pkts512to1023Octets
RO 0x0
■ Bit 0—The number of receive or transmit
frames between the length of 512 and
1,023 bytes, including the CRC field but
excluding the preamble and SFD bytes. This
count includes good, errored, and invalid
frames.
■ 36-bit width register:
■ 0x0C2A and 0x0C2B = bits [31:0]
■ 0x1C2A and 0x1C2B = bits [35:32]
0x0C2B
0x1C2A
tx_stats_etherStats
Pkts512to1023Octets 0x1C2B
0x0C2C
rx_stats_etherStat
Pkts1024to1518Octets
RO 0x0
■ Bit 0—The number of receive or transmit
frames between the length of 1,024 and
1,518 bytes, including the CRC field but
excluding the preamble and SFD bytes. This
count includes good, errored, and invalid
frames.
■ 36-bit width register:
■ 0x0C2C and 0x0C2F = bits [31:0]
■ 0x1C20 and 0x1C21 = bits [35:32]
0x0C2F
0x1C20
tx_stats_etherStat
Pkts1024to1518Octets 0x1C21
0x0C2E
rx_stats_etherStats
Pkts1519toXOctets
RO 0x0
■ Bit 0—The number of receive or transmit
frames equal or more than the length of
1,519 bytes, including the CRC field but
excluding the preamble and SFD bytes. This
count includes good, errored, and invalid
frames.
■ 36-bit width register:
■ 0x0C2E and 0x0C2F = bits [31:0]
■ 0x1C2E and 0x1C2F = bits [35:32]
0x0C2F
0x1C2E
tx_stats_etherStats
Pkts1519toXOctets 0x1C2F
Table 8–2. MAC Registers (Part 13 of 15)
Word
Offset
Register Name Access
Reset
Value
Description