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2 lan ground plane separation, 12 lpc (low pin count interface), 1 signal description – IEI Integration ICE-DB-9S User Manual

Page 87: 12 lpc (l, Ount, Nterface

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ICE Module

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4.11.4.2 LAN Ground Plane Separation

Isolated separation between the analog ground plane and digital ground plane is

recommended. If this is not implemented properly then bad ground plane partitioning

could cause serious EMI emissions and degrade analog performance due to bouncing

noise. The plane area underneath the magnetic module should be left void. The void

area is to keep transformer induced noise away from the power and system ground

planes. The isolated ground, also called chassis ground, connects directly to the fully

shielded RJ-45 connector. For better isolation it is also important to maintain a gap

between chassis ground and system ground that is wider than 60mils. For ESD

protection a 3kV high voltage capability capacitor is recommended to connect to this

chassis ground for ESD protection. Additionally, a ferrite bead can be placed parallel

to the capacitor.

4.12 LPC (Low Pin Count Interface)

The Low Pin Count Interface was defined by the Intel Corporation to facilitate the

industries transition toward legacy free systems. It allows the integration of

low-bandwidth legacy I/O components within the system, which are typically provided

by a Super I/O controller. Furthermore, it can be used to interface Firmware Hubs,

Trusted Platform Module (TPM) devices and Embedded Controller solutions. Data

transfer on the LPC bus is implemented over a 4 bit serialized data interface, which

uses a 33MHz LPC bus clock. For more information about LPC bus refer to the 'Intel

Low Pin Count Interface Specification Revision 1.1'.

4.12.1 Signal Description

Since COM Express is designed to be a legacy free standard for embedded modules,

it does not support legacy functionality such as PS/2 keyboard/mouse, serial and

parallel ports. Instead it provides an LPC interface that can be used to add peripheral

devices to the carrier board design. The reduced pin count of the LPC interface makes

it easy to implement such devices. All corresponding signals can be found on the

modules connector rows A and B.