IEI Integration ICE-DB-9S - Manual (Page 74)

Page 61
ICE Module
Separate signal traces into similar categories, and route similar signal traces
together (such as routing differential pairs together).
Keep USB 2.0 signals clear of the core logic set. High current transients are
produced during internal state transitions and can be very difficult to filter out.
4.6 LVDS
4.6.1 Signal Description
Table 4-15 shows COM Express LVDS and LCD signals, including pin number,
signals, I/O and descriptions.
Table 4-15: LVDS Signals Description
Pin Signal I/O Description
A71
A72 LVDS_A0+
LVDS_A0- O LVDS channel A differential signal pair 0
A73
A74 LVDS_A1+
LVDS_A1- O LVDS channel A differential signal pair 1
A75
A76 LVDS_A2+
LVDS_A2- O LVDS channel A differential signal pair 2
A78
A79 LVDS_A3+
LVDS_A3- O LVDS channel A differential signal pair 3
A81
A82 LVDS_A_CK+
LVDS_A_CK- O LVDS channel A differential clock pair
B71
B72 LVDS_B0+
LVDS_B0- O LVDS channel B differential signal pair 0
B73
B74 LVDS_B1+
LVDS_B1- O LVDS channel B differential signal pair 1
B75
B76 LVDS_B2+
LVDS_B2- O LVDS channel B differential signal pair 2
B77
B78 LVDS_B3+
LVDS_B3- O LVDS channel B differential signal pair 3
B81
B82 LVDS_B_CK+
LVDS_B_CK- O LVDS channel B differential clock pair
A77 LVDS_VDD_EN O 3.3V
CMOS LVDS flat panel power enable.
B79 LVDS_BKLT_EN O 3.3V
CMOS LVDS flat panel backlight enable high active signal
B83 LVDS_BKLT_CTRL O 3.3V
CMOS LVDS flat panel backlight brightness control
A83 LVDS_I2C_CK O 3.3V
CMOS DDC I2C clock signal used for flat panel detection
and control.
A84 LVDS_I2C_DAT I/O 3.3V
OD CMOS DDC I2C data signal used for flat panel detection
and control.