IEI Integration ICE-DB-9S - Manual (Page 100)

Page 87
ICE Module
5.1 Chapter Overview
A brief description of the Printed Circuit Board (PCB) for COM Express based board is
provided in this section. From a cost- effectiveness point of view, a four-layer board is
the target platform for the motherboard design. For better quality, a six-layer or
8-layer board is preferred. This chapter also provides the ATX/AT power supply design
recommendation for customer’s reference. IEI ICE module carrier board use 4-layer
PCB stack.
5.2 Microstrip or Stripline
Either edge-coupled microstrip, edge-coupled stripline, or broad-side striplines are
recommended for designs with differential signals. Designs with microstrip lines offer
the advantage that a lower number of layers can be used. Also, with microstrip lines it
may be possible to route from a connector pad to the device pad without any via. This
provides better signal quality on the signal path that connects devices. A limitation of
microstrip lines is that they can only be routed on the two outside layers of the PCB,
thus routing channel density is limited.
Stripline may be either edge-coupled or broad-side coupled lines. Stripline designs
provide additional shielding since they are embedded in the board stack and are
typically sandwiched between ground and power planes. This reduces radiation and
coupling of noise onto the lines. Striplines have the disadvantage that they require the
use of vias to connect to them.
5.3 PCB Stackup Example
It is recommended to use PCB's with at least a 4-layer stackup where the impedance
controlled layer 1 (top layer) is used for differential signals and layer 4 (bottom layer)
for other periodic signals (CMOS/TTL). The dedicated power planes (layer 2 – GND
and layer 3 – VCC) are typically required for high-speed designs. The solid ground
plane is necessary to establish a controlled (known) impedance for the transmission
line interconnects. A narrow spacing between power and ground planes will
additionally create an excellent high frequency bypass capacitance. The following
example shows a four layer PCB stackup using microstrip trace routing. A good rule to
follow for microstrip designs is to keep S < W and S < H (“H” = space between
differential signal layers and the reference plane). The best practice is to use the
closest spacing, “S,” allowed by your PCB vendor and then adjust trace widths, “W,” to
control differential impedance.