15 v15 - trtw read to write delay (same rank) – Teledyne LeCroy Kibra DDR User Manual
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Kibra DDR Protocol Analyzer User Manual
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DDR3 and DDR4 JEDEC Timing Violations Summary
Teledyne LeCroy
5.1.15
V15 - tRTW READ to WRITE delay (same rank)
Defines the interval between Read command and issuing a Write Command to the same
Rank. This is defined for BC:4 = CL‐CWL+2+CCD/2; or BL:8 = CL‐CWL+2+ CCD
5.1.16
V16 - tdrRTW READ to WRITE delay (different rank, same DIMM)
Defined as the interval between a READ command and a WRITE command to a different
rank in same DIMM. Timing between commands to a different rank should be vendor
specified.
5.1.17
V17 - tddRTW READ to WRITE delay (different DIMM)
Defined as the interval between a READ command and a WRITE command to a different
DIMM. Timing between commands to a different rank or DIMM should be vendor
specified.
5.1.18
V18 - tWTR WRITE to READ delay ( DDR3 - same rank) (DDR4 - same bank
group)
Defines the minimum delay from start of WRITE command to READ command. In case of
BC 4 mode, the internal write operation starts two clock cycles earlier than for the BL8
mode. This means that the starting point for tWR and tWTR will be pulled in by two clocks
when BC:4 is used. This is defined for BC:4 CWL+WTR(speed) + 2; or BL:8 =
CWL+WTR(speed) + 4. The formula is shown as tWTRx = CWL + tWTR[Spec] + (BL/2).
5.1.19
V19 - tdrWTR WRITE to READ delay (different rank, same DIMM)
Defined as the interval between a WRITE command and a READ command to a different
rank. Timing between commands to a different rank should be vendor specified.
5.1.20
V20 - tddWTR WRITE to READ delay (different DIMM)
Defined as the interval between a WRITE command and a READ command to a different
DIMM. Timing between commands to a different rank or DIMM should be vendor
specified.
5.1.21
V21 - tWTW WRITE to WRITE delay ( DDR3 - same rank) (DDR4 - same bank
group)
Defined as the interval between a WRITE command and the next Write command to the
same rank. This is calculated based on Write Latency (AL + CWL) ‐ tWPRE. This is also
known as CAS to CAS delay (tCCD).