Teledyne LeCroy Kibra DDR - Manual (Page 13)

Kibra DDR Protocol Analyzer User Manual 11
Kibra 380 or Kibra 480 Overview Teledyne LeCroy
1.1.4 Difference between Kibra 380 or Kibra 480
1. Kibra 480 supports both DDR3 and DDR4 Interposers. Kibra 380 only supports DDR3
interposers.
2. The Kibra 380 version of the interposers requires a stable DIMM_CLK to properly
sample the DIMM signals. If the DIMM_CLK is not running, the probe will require
6us after the DIMM_CLK resumes before proper capture occurs. This can occur
when recording DDR traffic during platform boot or during self refresh mode. This
limitation can cause RC and MRS commands to be missed.
The Kibra 480 does not have this limitation.
CMD/ADD/CNTRL Bus and Process JEDEC Protocol
The Analyzer observes CMD/ADD/CNTRL bus and processes JEDEC protocol requirements
in real‐time.
Errors can be seen in the Waveform view or the Listings view as well as in the Traffic
Summary. Errors listed in the Traffic Summary have a Hyperlink directly to the Waveform
and Listing view to allow quick viewing of errors.
Clock-Based Timing
The Analyzer features clock‐based timing. The clock times are based on the nominal
DIMM speed selected in the Recording Options and samples are synchronized to the
DIMM clock.
DIMM Slot Protocol
The Kibra 380 or Kibra 480 are able to track the DIMM slot protocol. They also have the
option to gather control signals from a second DIMM slot.
1.1.5 Trigger
Provides triggers for Command Ordering Violations and State Violations as well as user
selectable commands or command sequences. Trigger markers are accurate to 
clocks of the triggered event.