Artesyn ATCA-7365 Installation and Use (May 2014) - Manual (Page 201)

Maps and Registers
ATCA-7365 Installation and Use (6806800K65M) 201
6.4.10.6 OS IPMC Watchdog Timeout Register
When the IPMC Watchdog Timeout: bit of IPMC Watchdog Timeout Register is set the OS IPMC
Watchdog Timeout bit is set. The OS clears this status bit, writing one.
5 CPU_RST_ CPU Reset signal from CPU
1: Reset occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r
6 XDP0_DBRST_ CPU Debugger reset
1: Reset occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r
7 IPMC_RST_ REQ_ Payload Reset from IPMC.
1: Reset occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r
Table 6-52 Reset Source Register (continued)
Address Offset: 0x14
Bit Description Default Access
BIOS should never write to this register.
Table 6-53 OS IPMC Watchdog Timeout Register
Address Offset: 0x15
Bit Description Default Access
0 OS IPMC Watchdog Timeout:
1: IPMC Watchdog Timeout occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r
1 OS IPMC Pre-Timeout
1: IPMC Pre-Timeout occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r
7:2 Reserved 0 r