Artesyn ATCA-7365 Installation and Use (May 2014) - Manual (Page 122)

BIOS
ATCA-7365 Installation and Use (6806800K65M) 122
4.7.2 Spare Channel Mode
In Spare Channel Mode, Channel 0 and 1 are active channels and Channel 2 is the spare of the
other two channels. The spare channel is held in reserve and is not available as system memory.
The spare channel must have identical population to the channel being copied from. This
means that all three channels must have identical population with regards to size and
organization. The Memory Controller will maintain correctable ECC error counters for each
DIMM in the system that can either trigger an SMI event or be periodically polled by software
to determine whether a high error rate is happening. SMI Software can then configure the
Integrated Memory Controller to copy contents from one channel to another.
4.7.3 Mirrored Channel Mode
The Integrated Memory Controller supports mirroring across channels. DIMM organization in
each slot of one channel must be identical to the DIMM in the corresponding slot of the other
channel. When mirroring is enabled, the memory image in Channel 0 is maintained similar to
Channel 1. DIMMs in Channel 2 are unused.
Uncorrectable errors are logged and signaled as correctable, but change the channel state to
"Disabled", and the working partner to "Redundancy Loss".
4.7.4 Lockstep Channel Mode
The Lockstep configuration requires a minimum of two DIMMs, one in Channel 0 and one in
Channel 1. Channel 2 is not used in Lockstep Channel Mode. The ECC DRAM on each DIMM is
mapped in to two adjacent symbols so that any failure of the DRAM can be corrected. The
correction capabilities in lockstep mode are:
 Correction of any x4 or x8 DRAM device failure.
 Detection of 99.986% of all single bit failures that occur in addition to an x8 DRAM failure.
The Memory Controller will detect a series of failures on a specific DRAM and use this
information in addition to the information provided by the code to achieve 100% detection
of these cases.
 Detection of all permutations of 2 x4 DRAM failures.