Artesyn ATCA-7365 Installation and Use (May 2014) - Manual (Page 200)

Maps and Registers
ATCA-7365 Installation and Use (6806800K65M) 200
6.4.10.5 OS Reset Source Register
The OS Reset Source Register stores the source of the most recent reset as it is done in the BIOS
Reset Source Register. A one in the register bit indicates that the associated reset has occurred.
If more than one reset occurs from different sources without clearing the corresponding
register bits, one can not determine the most recent reset source since more than one bit will
be set. The same situation will happen, if two reset sources go active at the same time.
Table 6-51 BIOS Push Button Enable Register
Address Offset: 0x13
Bit Description Default Access
7:0 BIOS Push Button Enable Register - LPC: w
BIOS should never write to this register.
Table 6-52 Reset Source Register
Address Offset: 0x14
Bit Description Default Access
0 PWR_GOOD Payload Power-on reset
1: Reset occurred PWR_GOOD:1 LPC: r/w1c
IPMC: r
1 XDP0_BRD_PWROK CPU Debugger System reset request
1: Reset occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r
2 PB_RST_ face plate push button reset
1: Reset occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r
3 XDP1_DBRST_ CPU Debugger reset
1: Reset occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r
4 RTM_PB_RST_ Reset key at RTM
1: Reset occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r