Artesyn ATCA-7365 Installation and Use (May 2014) - Manual (Page 165)

Maps and Registers
ATCA-7365 Installation and Use (6806800K65M) 165
6.3.1 Register Decoding
The FPGA registers may be accessed from the host or the IPMC. For the host the LPC bus
interface is used. The IPMC uses an SPI interface.
0 or 1 Default value after PWR_GOOD is valid or after ICH_PLTRST
deassertion.
Undef. Undefined value
: 0 or 1 Default value after deassertion of the reset signal .
Ext. External Reset Source. Default depends on external logic level.
Table 6-5 Register Access Type
Access Description
r Read only
w Write only
r/w Read and write
w1c Write-1-to-clear, ignore bit while reading
r/w1c Read and write-1-to-clear, write 0 has no effect
r/w1s Read and write-1-to-set, write 0 has no effect
r/w1t Read and write-1-to-toggle, write 0 has no effect
LPC: The prefix “LPC:” signals that the access is restricted to the LPC
interface.
E. g.: LPC: r/w means that the register bit is read/writable from the
LPC interface
IPMC: The prefix “IPMC:” signals that the access is restricted to the IPMC
SPI interface.
E. g.: IPMC: r/w means that the register bit is read/writable from
IPMC SPI
interface
Table 6-4 Register Default (continued)
Default Description