Artesyn ATCA-7365 Installation and Use (May 2014) - Manual (Page 198)

Maps and Registers
ATCA-7365 Installation and Use (6806800K65M) 198
6.4.10.2 Reset Mask Register
The reset mask register enables or disables forwarding of a reset source to reset output signal.
Only Push Button Resets requests are affected by the reset mask register. The register default
values are latched when PWR_GOOD is asserted. This register can be read or written by the
host CPU. A one in the register bit indicates that the associated reset is enabled. A zero
indicates that the associated reset source is masked.
7 IPMC_RST_ REQ_ Payload Reset from IPMC.
1: Reset occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r
Table 6-48 BIOS Reset Source Register (continued)
Address Offset: 0x10
Bit Description Default Access
Table 6-49 Reset Mask Register
Address Offset: 0x11
Bit Description Default Access
0 Reserved PWR_GOOD:1 r
1 Spare switch SW3.4 PWR_GOOD:0 r
2 PB_RST_ face plate push button reset
1: enabled
0: disabled PWR_GOOD:0 r/w
3 Reserved PWR_GOOD:0 r
4 RTM_PB_RST_ Reset key at RTM
1: enabled
0: disabled PWR_GOOD:0 r/w
7:5 Reserved PWR_GOOD:0 r