Table 6-14, Super io device revision register, Table 6-15 – Artesyn ATCA-7365 Installation and Use (May 2014) User Manual
Page 171: Super io lpc control register, Table 6-16, Maps and registers
Maps and Registers
ATCA-7365 Installation and Use (6806800K65M)
171
Table 6-14 Super IO Device Revision Register
Index Address: 0x21
Bit
Description
Default
Access
7:0
Device Revision
0x01
LPC: r
Table 6-15 Super IO LPC Control Register
Index Address: 0x28
Bit
Description
Default
Access
0
LPC Bus Wait States:
1: Long wait states (sync 6)
1
LPC: r
1
Reserved
0
LPC: r
Table 6-16 Global Super IO SERIRQ and Pre-divide Control Register
Index Address: 0x29
Bit
Description
Default
Access
0
SERIRQ enable:
0: disabled. Serial interrupts disabled.
1: enabled. Logical devices participate in interrupt
generations.
0
LPC: r/w
1
SERIRQ Mode:
1: Continuous Mode
1
LPC: r
3:2
UART Clock pre-divide
00: divide by 1
01: divide by 8
10: divide by 26 (CLK_UART is 48 MHz)
11: reserved
0
LPC: r/w
7:4
Reserved
0
LPC: r