Artesyn ATCA-7365 Installation and Use (May 2014) - Manual (Page 197)

Maps and Registers
ATCA-7365 Installation and Use (6806800K65M) 197
6.4.10 Reset Registers
6.4.10.1 BIOS Reset Source Register
The BIOS Reset Source Register stores the source of the most recent reset. A one in the register
bit indicates that the associated reset has occurred. If more than one reset occurs from
different sources without clearing the corresponding register bits, one can not determine the
most recent reset source since more than one bit will be set. The same situation will happen, if
two reset sources go active at the same time.
OS should never write to this register.
Table 6-48 BIOS Reset Source Register
Address Offset: 0x10
Bit Description Default Access
0 PWR_GOOD Payload Power-on reset
1: Reset occurred PWR_GOOD:1 LPC: r/w1c
IPMC: r
1 XDP0_BRD_PWROK CPU Debugger System reset request
1: Reset occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r
2 PB_RST_ face plate push button reset
1: Reset occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r
3 XDP1_DBRST_ CPU Debugger reset
1: Reset occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r
4 RTM_PB_RST_ Reset key at RTM
1: Reset occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r
5 CPU_RST_ CPU Reset signal from CPU
1: Reset occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r
6 XDP0_DBRST_ CPU Debugger reset
1: Reset occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r