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Table 3-9, Zone 3 connector j32 pin assignment, Controls, indicators, and connectors – Artesyn ATCA 7370 / ATCA 7370-S Installation and Use (June 2014) User Manual

Page 70

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Controls, Indicators, and Connectors

ATCA-7370/ATCA-7370-S Installation and Use (6806800P54F)

70

6

PCIE_CPU1_

RX10+

PCIE_CPU1_

RX10-

PCIE_CPU1_

TX10+

PCIE_CPU1_

TX10-

PCIE_CPU1_

RX11+

PCIE_CPU1

_RX11-

PCIE_CPU1_T

X11+

PCIE_CPU1_T

X11-

7

PCIE_CPU1_

RX12+

PCIE_CPU1_

RX12-

PCIE_CPU1_

TX12+

PCIE_CPU1_

TX12-

PCIE_CPU1_

RX13+

PCIE_CPU1

_RX13-

PCIE_CPU1_T

X13+

PCIE_CPU1_T

X13-

8

PCIE_CPU1_

RX14+

PCIE_CPU1_

RX14-

PCIE_CPU1_

TX14+

PCIE_CPU1_

TX14-

PCIE_CPU1_

RX15+

PCIE_CPU1

_RX15-

PCIE_CPU1_T

X15+

PCIE_CPU1_T

X15-

9

PCIE

CLK

CLK_100M_A

B+

CLK_100M_

AB-

CLK_100M_

CD+

CLK_100M_

CD-

10

Table 3-9 Zone 3 Connector J32 Pin Assignment

J32

Row

#

Interf

ace

Col AB

Col CD

Col EF

Col GH

1

PCIE

Port9

PCIE9_RP[0]

PCIE9_RN[0]

PCIE9_TP[0]

PCIE9_TN[0]

PCIE9_RP[1]

PCIE9_RN[1]

PCIE9_TP[1]

PCIE9_TN[1]

2

PCIE9_RP[2]

PCIE9_RN[2]

PCIE9_TP[2]

PCIE9_TN[2]

PCIE9_RP[3]

PCIE9_RN[3]

PCIE9_TP[3]

PCIE9_TN[3]

3

PCIE

Port8

PCIE8_RP[0]

PCIE8_RN[0]

PCIE8_TP[0]

PCIE8_TN[0]

PCIE8_RP[1]

PCIE8_RN[1]

PCIE8_TP[1]

PCIE8_TN[1]

4

PCIE8_RP[2]

PCIE8_RN[2]

PCIE8_TP[2]

PCIE8_TN[2]

PCIE8_RP[3]

PCIE8_RN[3]

PCIE8_TP[3]

PCIE8_TN[3]

5

PCIE

Port7

PCIE7_RP[0]

PCIE7_RN[0]

PCIE7_TP[0]

PCIE7_TN[0]

PCIE7_RP[1]

PCIE7_RN[1]

PCIE7_TP[1]

PCIE7_TN[1]

6

PCIE7_RP[2]

PCIE7_RN[2]

PCIE7_TP[2]

PCIE7_TN[2]

PCIE7_RP[3]

PCIE7_RN[3]

PCIE7_TP[3]

PCIE7_TN[3]

7

PCIE

Port6

PCIE6_RP[0]

PCIE6_RN[0]

PCIE6_TP[0]

PCIE6_TN[0]

PCIE6_RP[1]

PCIE6_RN[1]

PCIE6_TP[1]

PCIE6_TN[1]

8

PCIE6_RP[2]

PCIE6_RN[2]

PCIE6_TP[2]

PCIE6_TN[2]

PCIE6_RP[3]

PCIE6_RN[3]

PCIE6_TP[3]

PCIE6_TN[3]

9

PCIE

CLK

PCIE9_CLKP

PCIE9_CLKN

PCIE8_CLKP

PCIE8_CLKN

PCIE7_CLKP

PCIE7_CLKN

PCIE6_CLKP

PCIE6_CLKN

10

V12P

V12P

V12P

PS0_N

Table 3-8 Zone 3 Connector J31 Pin Assignment

J31

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