Artesyn ATCA 7370 / ATCA 7370-S Installation and Use (June 2014) - Manual (Page 142)

Maps and Registers
ATCA-7370/ATCA-7370-S Installation and Use (6806800P54F) 142
6.2.5.8 Line Status Register (LSR)
This register provides status information to the processor concerning the data transfers. Bits 5
and 6 show information about the transmitter section. The rest of the bits contain information
about the receiver.
In non-FIFO mode, three of the LSR register bits, parity error, framing error, and break
interrupt, show the error status of the character that has just been received. In FIFO mode,
these three bits of status are stored with each received character in the FIFO. LSR shows the
status bits of the character at the top of the FIFO. When the character at the top of the FIFO has
errors, the LSR error bits are set and are not cleared until software reads LSR, even if the
character in the FIFO is read and a new character is now at the top of the FIFO.
Bits one through four are the error conditions that produce a receiver line status interrupt when
any of the corresponding conditions are detected and the interrupt is enabled. These bits are
not cleared by reading the erroneous byte from the FIFO or receive buffer.
4 Local loop back diagnostic control
When loop back is activated: Transmitter
TXD is set high. Receiver RXD is
disconnected. Output of Transmitter Shift
register is looped back into the receiver shift
register input. Modem control inputs are
disconnected Modem control outputs are
internally connected to modem control
inputs. Modem control outputs are forced to
the inactive (high) levels:
1: Loop back mode activated
0: Normal operation 0 LPC: r/w
5 Autoflow control enable (AFE):
1: Autoflow control enabled (auto-RTS# and
auto-CTS# or auto-CTS# only enabled)
0: Autoflow control disabled 0 LPC: r/w
7:6 Reserved 0 LPC: r
Table 6-36 Modem Control Register (MCR) (continued)
LPC IO Address: Base + 4
Bit Description Default Access