Artesyn ATCA 7370 / ATCA 7370-S Installation and Use (June 2014) - Manual (Page 133)

Maps and Registers
ATCA-7370/ATCA-7370-S Installation and Use (6806800P54F) 133
6.2.4 UART1 and UART2 Register Map
6.2.4.1 UART Register Overview
Table 6-1 "Interrupt Source Signals List" shows the registers and their addresses as offsets of a
base address for one or two UART.
The most significant bit of the Serial Line Control Register (SCR) is the Divisor Latch Bit (DLAB).
Its state effects the selection of certain UART registers. The DLAB bit must be set high by the
system software to access the Baud Rate Generator Divisor Latches (DLL and DLM)
Table 6-27 UART Register Overview
LPC IO Address DLAB Bit value Description
Base 0 Receiver Buffer (RBR). Read Only
Base 0 Transmitter Holding (THR). Write Only.
Base + 1 0 Interrupt Enable Register (IER)
Base + 2 X Interrupt Identification Register (IIR). Read Only
Base + 2 X FIFO Control Register (FCR). Write Only.
Base + 3 X Line Control Register (LCR)
Base + 4 X Modem Control Register (MCR)
Base + 5 X Line Status Register (LSR). Read Only
Base + 6 X Modem Status Register (MSR). Read Only
Base + 7 X Scratch Pad Register (SCR).
Base 1 Divisor Latch LSB (DLL)
Base + 1 1 Divisor Latch MSB (DLM)