Artesyn ATCA 7370 / ATCA 7370-S Installation and Use (June 2014) - Manual (Page 141)

Maps and Registers
ATCA-7370/ATCA-7370-S Installation and Use (6806800P54F) 141
6.2.5.7 Modem Control Register (MCR)
The MCR is an 8-bit register that controls the interface with the modem or data set (or any
peripheral device emulating a modem).
7 Divisor latch access bit (DLAB)
Bit 7 must be set to access the divisor latches
of the baud generator during a read or write.
Bit 7 must be cleared during a read or write
to access the RBR, THR, or IER.:
1: Access to DLL and DLM registers
0: Access to RBR, THR and IER registers 0 LPC: r/w
Table 6-35 Line Control Register (LCR) (continued)
LPC IO Address: Base + 3
Bit Description Default Access
Table 6-36 Modem Control Register (MCR)
LPC IO Address: Base + 4
Bit Description Default Access
0 Data terminal ready (DTR#) output control:
1: DTR# output in low (active) state
0: DTR# output in high state 0 LPC: r/w
1 Request to send (RTS#) output control:
1: RTS# output in low (active) state
0: RTS# output in high state 0 LPC: r/w
2 User output control signal (OUT1#):
1: OUT1# output in high state
0: OUT1# output in low state
Not supported 0 LPC: r/w
3 User output control signal (OUT2#):
1: OUT2# output in high state
0: OUT2# output in low state
Not supported 0 LPC: r/w