Artesyn ATCA 7370 / ATCA 7370-S Installation and Use (June 2014) - Manual (Page 134)

Maps and Registers
ATCA-7370/ATCA-7370-S Installation and Use (6806800P54F) 134
6.2.5 UART Registers DLAB=0
6.2.5.1 Receiver Buffer Register
In non-FIFO mode, the Receiver Buffer Register (RBR) holds the character received by the
UART’s Receive Shift Register. If less than 8-bits are received, the bits are right-justified and the
leading bits are zeroed. Reading the register empties the register and resets the data ready
(DR) bit in the line status register to zero. Other bits, errors or otherwise, are not cleared. In
FIFO mode, this register latches the value of the data byte at the top of the FIFO.
6.2.5.2 Transmitter Holding Register (THR)
This register holds the next data byte to be transmitted. When the transmit shift register
becomes empty, the contents of the THR is loaded into the shift register. The transmit data
request (TDRQ) bit in the line status register is set to one.
Writing to THR while in FIFO mode puts THR to the top. The data at the bottom of the FIFO is
loaded to the shift register when it is empty.
Table 6-28 Receiver Buffer Register (RBR) if DLAB=0
LPC IO Address: Base
Bit Description Default Access
7:0 Receiver Buffer register (RBR) Undef. LPC: r
Table 6-29 Transmitter Holding Register (THR) if DLAB=0
LPC IO Address: Base
Bit Description Default Access
7:0 Transmitter Holding register (THR) Undef. LPC: w