Artesyn ATCA 7370 / ATCA 7370-S Installation and Use (June 2014) - Manual (Page 172)

Maps and Registers
ATCA-7370/ATCA-7370-S Installation and Use (6806800P54F) 172
6.3.19 Scratch Register
6.3.20 POST Code Register
The FPGA provides an 8-bit wide register to store POST codes to the LPC I/O address 0x80. The
two nibbles of the register are converted to seven segment codes and are displayed as two hex
values by two seven-segment LED displays, which can be read by IPMC at SPI address 0x7F.
6.4 Standard Status Codes
Table 6-72 LPC Scratch Registers
Address Offset: 0x76-7D
Bit Description Default Access
7:0 LPC Scratch bits. 0x00 LPC: r/w
IPMC: r
Table 6-73 POST Code Register
Address Offset: 0x7F
Bit Description Default Access
7:0 POST codes from host 0x00 IPMC: r
Table 6-74 Component Status Codes
Status Code Code Symbol
0x20 POSTCODE_CC_VARIABLE_SERVICES
0x21 POSTCODE_CC_KEYBOARD_CONTROLLER
0x22 POSTCODE_CC_BOOT_MODE
0x23 POSTCODE_CC_S3_SUPPORT