Artesyn ATCA 7370 / ATCA 7370-S Installation and Use (June 2014) - Manual (Page 121)

Maps and Registers
ATCA-7370/ATCA-7370-S Installation and Use (6806800P54F) 121
The chipset has NMI Status and Control Register and the NMI Enable Register. Both can be used
to configure the relevant settings and get the status report. Software can also set NMI2SMI_EN
bit in TC01 Control Register to force all NMIs to instead cause SMI. The functionality of this bit
is dependent upon the settings of the NMI_EN bit and the GBL_SMI_EN bit, as detailed in the
succeeding table.
IPMC can initiate a NMI request to processor to cause a warm-reset when the Payload-
Watchdog in IPMC is timeout or when IPMC receives a command from shelf-manager.
In Intel Xeon E5-2648L Processor, either SMI or NMI interrupts can be enabled in
MC_SMI_CNTRL register. The type of interrupt trigger is based on the following conditions or
scenarios:
 A DIMM error counter exceeds the threshold
 Redundancy is lost on a mirrored configuration or
 A sparing operation completes.
 Warm reset request.
This register is set by hardware once operation is complete. Bit is cleared by hardware when a
new operation is enabled. An SMI is generated when this bit is set due to a sparing copy
completion event.
NMI_EN GBL_SMI_EN Description
0b 0b No SMI# at all because GBL_SMI_EN = 0
0b 1b SMI# will be caused due to NMI events
1b 0b No SMI# at all because GBL_SMI_EN = 0
1b 1b No SMI# due to NMI because NMI_EN = 1