11 payload power-button register, 12 reset registers, 1 reset mask register – Artesyn ATCA 7370 / ATCA 7370-S Installation and Use (June 2014) User Manual
Page 158: Table 6-51, Payload power-button register, Table 6-52, Reset mask register, Maps and registers
Maps and Registers
ATCA-7370/ATCA-7370-S Installation and Use (6806800P54F)
158
6.3.11 Payload Power-Button Register
6.3.12 Reset Registers
6.3.12.1 Reset Mask Register
The reset mask register enables or disables forwarding of a reset source to reset output signal.
Only Push Button Resets requests are affected by the reset mask register. The register default
values are latched when RST_N is asserted. This register can be read or written by the host CPU.
A one in the register bit indicates that the associated reset is enabled. A zero indicates that the
associated reset source is masked.
Table 6-51 Payload Power-Button Register
Address Offset: 0x09
Bit
Description
Default
Access
0
FPGA_PCH_PWRBTN_N
1
IPMC: r/w
7:1
Reserved
0
r
Table 6-52 Reset Mask Register
Address Offset: 0x0F
Bit
Description
Default
Access
0
Reserved
0
r
1
Reserved
0
r
2
Enable front board push button reset
payload
1: enabled
0: disabled
0
LPC: r/w
IPMC: r
3
Enable IPMC reset payload
1: enabled
0: disabled
1
LPC: r
IPMC: r/w