Artesyn ATCA 7370 / ATCA 7370-S Installation and Use (June 2014) - Manual (Page 124)

Maps and Registers
ATCA-7370/ATCA-7370-S Installation and Use (6806800P54F) 124
6.2.1.1 LPC Decoding
The LPC bus supports different protocols.
6.2.1.1.1 LPC I/O Decoding
The LPC interface responds to LPC I/O accesses listed in the Table 6-8 . All other LPC I/O accesses
are ignored.
All LPC I/O accesses to the address range REGISTERS are decoded by the LPC core.
6.2.1.1.2 LPC Memory Decoding
The LPC interface never responds to LPC Memory accesses.
6.2.1.1.3 LPC Firmware Decoding
The LPC interface never responds to LPC Firmware accesses.
Table 6-8 LPC I/O Register Map Overview
Base
Address
Address Size
Address
Range
Name
Description
0x4E 2 SIW Super IO Configuration Registers for Index and Date
0x80 1 POSTCODE POST Code Register
BASE1 8 COM1 UART1. Serial Port 1 (Logical Device 4). BASE1 address is
set up during Super IO Configuration.
BASE2 8 COM2 UART2. Serial Port 2. (Logical Device 4). BASE2 address is
set up during Super IO Configuration.
0x600 128 REGISTERS FPGA Registers