Artesyn ATCA 7370 / ATCA 7370-S Installation and Use (June 2014) - Manual (Page 125)

Maps and Registers
ATCA-7370/ATCA-7370-S Installation and Use (6806800P54F) 125
6.2.1.2 SPI Register Decoding
All SPI accesses from the IPMC towards the FPGA with the SPI select signal BMC_SPI_S0_N
asserted are for the internal registers.
6.2.2 POST Code Register
The FPGA provides and 8-bit wide register to store POST codes to the LPC I/O address 0x80.
The IPMC may read the POST code using the SPI interface (with the signal BMC_SPI_S0_N
asserted) and the SPI address 0x7F.
Table 6-9 IPMC SPI Register
SPI Address Range Address Range Name Description
0x00 - 0x7F REGISTERS FPGA Registers
Table 6-10 POST Code Register
LPC I/O Address: 0x80
IPMC SPI Address: 0x7f
Bit Description Default Access
7:0 POST codes from host 0 LPC: r/w
IPMC: r