Altera Cyclone II DSP Development Board - Manual (Page 99)

Altera Corporation Reference Manual C–13
August 2006 Cyclone II DSP Development Board
EVM_CLKR0 G25 J25 EVM_A15
EVM_CLKX0 F24 J26 EVM_A11
EVM_CNTL0 M21 J3 PROTO_IO17
EVM_D0 V22 J4 PROTO_IO33
EVM_D1 AB25 J5 PROTO_IO0
EVM_D10 L21 J6 PROTO_IO37
EVM_D11 Y26 J7 PROTO_IO31
EVM_D12 K19 J8 PROTO_IO7
EVM_D13 W24 J9 1.2V
EVM_D14 K21 K1 PROTO_IO21
EVM_D15 U22 K10 1.2V
EVM_D16 K22 K11 1.2V
EVM_D17 V26 K12 1.2V
EVM_D18 K23 K13 1.2V
EVM_D19 U24 K14 1.2V
EVM_D2 M19 K15 1.2V
EVM_D20 J22 K16 GND
EVM_D21 U26 K17 GND
EVM_D22 J23 K18 1.2V
EVM_D23 T21 K19 EVM_D12
EVM_D24 H23 K2 DIG_LSB_A
EVM_D25 R24 K20 GND
EVM_D26 H24 K21 EVM_D14
EVM_D27 P24 K22 EVM_D16
EVM_D28 G23 K23 EVM_D18
EVM_D29 AB24 K24 EVM_A13
EVM_D3 AB26 K25 EVM_A9
EVM_D30 G24 K26 EVM_A7
EVM_D31 N23 K3 PROTO_IO25
EVM_D4 N20 K4 PROTO_IO35
EVM_D5 AA25 K5 PROTO_IO32
EVM_D6 M20 K6 PROTO_IO38
Table C–1. Cyclone II EP2C70F672-C6ES FPGA Pin-Outs (Part 13 of 22) Note (1)
Alphabetical by Signal Name Alphabetical by Pin Number
Schematic Signal Name Pin Number Pin Number Schematic Signal Name