Altera Cyclone II DSP Development Board - Manual (Page 98)

C–12 Reference Manual Altera Corporation
Cyclone II DSP Development Board August 2006
Introduction
EP2C_STATUSN R22 H2 VGA_B4
EPCS_USER_CSN Y23 H20 1.2V
EVM_A10 D26 H21 VGA_HSYNC
EVM_A11 J26 H22 GND
EVM_A12 D25 H23 EVM_D24
EVM_A13 K24 H24 EVM_D26
EVM_A14 D23 H25 EVM_A19
EVM_A15 J25 H26 EVM_DR0
EVM_A16 C25 H3 PROTO_IO26
EVM_A17 G26 H4 PROTO_IO34
EVM_A18 C24 H5 GND
EVM_A19 H25 H6 PROTO_IO1
EVM_A2 E25 H7 1.2V
EVM_A20 B25 H8 GND
EVM_A21 F26 H9 1.8V
EVM_A3 L24 J1 PROTO_IO19
EVM_A4 E26 J10 GND
EVM_A5 L25 J11 GND
EVM_A6 E24 J12 1.8V
EVM_A7 K26 J13 GND
EVM_A8 E23 J14 GND
EVM_A9 K25 J15 1.8V
EVM_ARDY W23 J16 GND
EVM_AREN P26 J17 GND
EVM_BEN0 F23 J18 1.2V
EVM_BEN1 M23 J19 3.3V
EVM_BEN2 F25 J2 PROTO_IO20
EVM_BEN3 M24 J20 EVM_FSR0
EVM_BWEN V23 J21 AUDIO_DIN
EVM_CEN2 J24 J22 EVM_D20
EVM_CEN3 AE25 J23 EVM_D22
EVM_CLKOUT2 P2 J24 EVM_CEN2
Table C–1. Cyclone II EP2C70F672-C6ES FPGA Pin-Outs (Part 12 of 22) Note (1)
Alphabetical by Signal Name Alphabetical by Pin Number
Schematic Signal Name Pin Number Pin Number Schematic Signal Name