Altera Cyclone II DSP Development Board User Manual
Page 85
Altera Corporation
Reference Manual
B–3
August 2006
Cyclone II DSP Development Board
EVM_D17
SRAM_D16
18
V26
EVM_D18
SRAM_D6
62
K23
EVM_D19
SRAM_D17
19
U24
EVM_D20
SRAM_D5
59
J22
EVM_D21
SRAM_D18
22
U26
EVM_D22
SRAM_D4
58
J23
EVM_D23
SRAM_D19
23
T21
EVM_D24
SRAM_D3
57
H23
EVM_D25
SRAM_D20
24
R24
EVM_D26
SRAM_D2
56
H24
EVM_D27
SRAM_D21
25
P24
EVM_D28
SRAM_D1
53
G23
EVM_D29
SRAM_D22
28
AB24
EVM_D30
SRAM_D0
52
G24
EVM_D31
SRAM_D23
29
N23
EVM_DMAC0
EVM_ADSPn
84
N24
EVM_OEn
SRAM_OEn
86
AA23
EVM_STAT0
SRAM_ADSCn
85
L20
GND
SRAM_A20
42
SRAM_CLK
SRAM_CLK_R
89
R25
SRAM_CE2
97
SRAM_CEn3
92
SRAM_DQP0
51
SRAM_DQP1
80
SRAM_DQP2
1
SRAM_DQP3
30
SRAM_GWn
88
SRAM_MODE
31
Note to
(1)
Blank cells indicate no connection.
Table B–1. Cyclone II to SSRAM Device Signal Changes (Part 3 of 3)
(1)
Cyclone II (U12) Signal
Name
SSRAM (U22) Signal
Name
SSRAM (U22) Pin
Cyclone II (U12) Pin
Name
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)