Altera Cyclone II DSP Development Board User Manual
Page 48
2–40
Reference Manual
Altera Corporation
Cyclone II DSP Development Board
August 2006
Memory Components
lists the pin connections between the SSRAM and the
Cyclone II pin number.
Table 2–23. SSRAM Device Pin-Outs (Part 1 of 2)
SSRAM Pin Name
SSRAM (U22)
Pin Number
Cyclone II
(U12) Pin
Number
SSRAM Pin Name
SSRAM (U22)
Pin Number
Cyclone II
(U12) Pin
Number
A0
37
K26
DQC25
3
AB26
A1
36
E24
DQC26
6
AA25
A10
99
D25
DQC27
7
AA26
A11
43
K24
DQC28
8
AA24
A12
44
D23
DQC29
9
Y26
A13
45
J25
DQC30
12
W24
A14
46
C25
DQC31
13
U22
A15
47
G26
DQD16
18
V26
A16
48
C24
DQD17
19
U24
A17
49
E26
DQD18
22
U26
A18
38
E25
DQD19
23
T21
A19
39
F26
DQD20
24
R24
A2
82
L25
DQD21
25
P24
A20
42
GND
DQD22
28
AB24
A3
33
H25
DQD23
29
N23
A4
81
L24
DQPA
51
A5
35
B25
DQPB
80
A6
100
E23
DQPC
1
A7
50
K25
DQPD
30
A8
34
D26
GW_n
88
A9
32
J26
MODE
31
ADSC_n
85
L20
NC_14
14
ADSP_n
84
N24
NC_16
16
ADV_n
83
M21
NC_66
66
BWA_n
93
F23
OE_n
86
AA23
BWB_n
94
M23
VDD
15
BWC_n
95
F25
VDD
41
BWD_n
96
M24
VDD
65
BWE_n
87
V23
VDD
91
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)