Altera Cyclone II DSP Development Board - Manual (Page 32)

2–24 Reference Manual Altera Corporation
Cyclone II DSP Development Board August 2006
User Interfaces
Table 2–17 lists the J37 (channel A) and J36 (channel B) jumper settings
used to select the A/D converter clock.
Figure 2–11 shows the J37 and J36 pin-outs listed in Table 2–17 . Pins 1 and
2 show an example jumper setting used to select the OSC clock.
Figure 2–11. J37 & J36 Pin Settings
Table 2–17. TI ADS5520 A/D Converter (U28 & U31) Clock Source Settings
Clock Source
Board
Reference
Schematic Signal Name
A/D Converter Clock Select
(J37 or J36) Jumper Setting
OSC clock OSC CLK_OSC_ADCA (Channel A)
CLK_OSC_ADCB (Channel B)
Pins 1 and 2
FPGA clock PLL FPGA_TO_ADC_CLK Pins 3 and 4
SMA clock (J27) SMA SMA_TO_ADC_CLK Pins 5 and 6
J37 & J36
Pin 2
OSC
PLL
SMA
Pin1