Altera Cyclone II DSP Development Board User Manual
Page 54
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2–46
Reference Manual
Altera Corporation
Cyclone II DSP Development Board
August 2006
Expansion Connectors
PROTO_IO31
J7
B_PROTO_IO31
J22.6
PROTO_IO32
K5
B_PROTO_IO32
J22.7
PROTO_IO33
J4
B_PROTO_IO33
J22.8
PROTO_IO34
H4
B_PROTO_IO34
J22.9
PROTO_IO35
K4
B_PROTO_IO35
J22.10
PROTO_IO36
L4
B_PROTO_IO36
J22.11
PROTO_IO37
J6
B_PROTO_IO37
J22.12
PROTO_IO38
K6
B_PROTO_IO38
J22.13
PROTO_IO39
K8
B_PROTO_IO39
J22.14
PROTO_IO40
C3
B_PROTO_IO40
J22.1
DC_INPUT
J23.1
3.3V
J23.5
3.3V
J23.7
3.3V
J23.15
3.3V
J23.17
3.3V
J23.19
GND
J15. 2
GND
J15.19
GND
J15.22
GND
J15.24
GND
J15.26
GND
J15.30
GND
J15.40
GND
J22.1
GND
J23.2
GND
J23.4
GND
J23.6
GND
J23.8
GND
J23.10
GND
J23.12
GND
J23.14
GND
J23.16
Table 2–24. Expansion Prototype Connector Pin Numbers - J15, J22 & J23 (Part 2 of 3)
Cyclone II (U12) Signal
Name
Cyclone II (U12) Pin
Number
Proto Debug Signal Name Proto Debug Pin Number
(1)
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)