Altera Cyclone II DSP Development Board User Manual
Page 57
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Altera Corporation
Reference Manual
2–49
August 2006
Cyclone II DSP Development Board
Cyclone II DSP Development Board Components
EVM_D12
U40.56
K19
EVM_D13
U40.55
W24
EVM_D14
U40.54
K21
EVM_D15
U40.53
U22
EVM_D16
U40.50
K22
EVM_D17
U40.49
V26
EVM_D18
U40.48
K23
EVM_D19
U40.47
U24
EVM_D2
U40.68
M19
EVM_D20
U40.46
J22
EVM_D21
U40.45
U26
EVM_D22
U40.44
J23
EVM_D23
U40.43
T21
EVM_D24
U40.40
H23
EVM_D25
U40.39
R24
EVM_D26
U40.38
H24
EVM_D27
U40.37
P24
EVM_D28
U40.36
G23
EVM_D29
U40.35
AB24
EVM_D3
U40.67
AB26
EVM_D30
U40.34
G24
EVM_D31
U40.33
N23
EVM_D4
U40.66
N20
EVM_D5
U40.65
AA25
EVM_D6
U40.64
M20
EVM_D7
U40.63
AA26
EVM_D8
U40.60
L19
EVM_D9
U40.59
AA24
EVM_DMAC0
U34.74
N24
EVM_DR0
U34.30
H26
EVM_DX0
U34.24
G21
EVM_FSR0
U34.29
J20
Table 2–25. TI-EVM Connector Pin-Outs (Part 3 of 4)
Schematic Signal
Name
TI-EVM Connector (U34, U40)
Pin Number
Cyclone II (U12) Pin
Number
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)