Altera Cyclone II DSP Development Board - Manual (Page 90)

C–4 Reference Manual Altera Corporation
Cyclone II DSP Development Board August 2006
Introduction
1.8V W9 AC21 DIMM_CK_P0
3.3V AA22 AC22 DIMM_CASN_R
3.3V AB5 AC23 VGA_R4
3.3V AD1 AC24
3.3V AD26 AC25 AUDIO_CSN
3.3V C1 AC26 EVM_INT2
3.3V C26 AC3 USER_LED4
3.3V F22 AC4 GND
3.3V F5 AC5 DIMM_A_R14
3.3V J19 AC6 DIMM_A_R6
3.3V L1 AC7 VREF
3.3V L26 AC8 DIMM_A_R1
3.3V M18 AC9 DIMM_DM2
3.3V M9 AD1 3.3V
3.3V N22 AD10 DIMM_DQ17
3.3V N5 AD11 DIMM_DQ21
3.3V P22 AD12 DIMM_DQ11
3.3V P5 AD13 PROTO_CLKOUT
3.3V R18 AD14 GND
3.3V R9 AD15 GND
3.3V T1 AD16 DIMM_DQ7
3.3V T26 AD17 DIMM_DQ5
3.3V V19 AD18 GND
3.3V V8 AD19 DIMM_CK_N0
ADC_A_D0 C5 AD2 AUDIO_SDIN
ADC_A_D1 C6 AD20 1.8V
ADC_A_D10 A23 AD21 DIMM_CK_N1
ADC_A_D11 B23 AD22 DIMM_CK_P2
ADC_A_D12 C22 AD23 DIMM_RESETN
ADC_A_D13 A22 AD24 ADC_SCLK
ADC_A_D2 B7 AD25 VGA_R2
ADC_A_D3 A8 AD26 3.3V
Table C–1. Cyclone II EP2C70F672-C6ES FPGA Pin-Outs (Part 4 of 22) Note (1)
Alphabetical by Signal Name Alphabetical by Pin Number
Schematic Signal Name Pin Number Pin Number Schematic Signal Name