Figure 2–24 – Altera Cyclone II DSP Development Board User Manual
Page 76
2–68
Reference Manual
Altera Corporation
Cyclone II DSP Development Board
August 2006
Power Supply
Figure 2–24. Cyclone II DSP Development Board Power Distribution Diagram
1.8V
Voltage
Select
1.8V
1.8V
1.8V
3.3V
3.3V
3.3V
J2
Digital Ground
J40
DAC Ground
J41
ADC Ground
DC Input
(40W)
(v8 03/18/05)
VCCA_PLL1
VCCA_PLL2
VCCA_PLL3
VCCA_PLL4
1A
1A
200mA
7A
F3
F2
F4
F1
F6
J4
J6
J5
J3
Single 3.3V Plane
Single 1.2V Plane
DAC Analog Plane
ADC Analog Plane
5V
DDR2 SDRAM DIMM
3A (1)
VTT_DIMM
VREF_DIMM
Passive
Filters
J39
VCCA_DAC
F7
F5
J42
VCCA_ADC
U8
Linear
Regulator
0.9V
U7
Linear
Regulator
1.2V
U23
Linear
Regulator
5.5V/3.3V
U10
Linear
Regulator
5V
U24
Linear
Regulator
3.3V
U2
Dual
Output
Switching
Regulator
1.8V
3.3V
(1)
6V
1.5A
(1)
3A
(1)
(1)
7A
(1)
(1)
1A
(1)
(1) Regulators can source up to the indicated current.
U9
Switching
Regulator
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)