Altera Cyclone II DSP Development Board User Manual
Page 40
2–32
Reference Manual
Altera Corporation
Cyclone II DSP Development Board
August 2006
Memory Components
DIMM_DQ55
DIMM_DQ55
227
C15
DIMM_DQ56
DIMM_DQ56
110
A18
DIMM_DQ57
DIMM_DQ57
111
B17
DIMM_DQ58
DIMM_DQ58
116
G16
DIMM_DQ59
DIMM_DQ59
117
G15
DIMM_DQ60
DIMM_DQ60
229
E15
DIMM_DQ61
DIMM_DQ61
230
A17
DIMM_DQ62
DIMM_DQ62
235
F15
DIMM_DQ63
DIMM_DQ63
236
F16
DIMM_DQ64
DIMM_DQ64
42
G9
DIMM_DQ65
DIMM_DQ65
43
C4
DIMM_DQ66
DIMM_DQ66
48
B5
DIMM_DQ67
DIMM_DQ67
49
D7
DIMM_DQ68
DIMM_DQ68
161
F9
DIMM_DQ69
DIMM_DQ69
162
B4
DIMM_DQ70
DIMM_DQ70
167
A5
DIMM_DQ71
DIMM_DQ71
168
C7
DIMM_DQS0
DIMM_DQS0
7
AF19
DIMM_DQS1
DIMM_DQS1
16
AE15
DIMM_DQS2
DIMM_DQS2
28
AE13
DIMM_DQS3
DIMM_DQS3
37
AE8
DIMM_DQS4
DIMM_DQS4
84
B8
DIMM_DQS5
DIMM_DQS5
93
C12
DIMM_DQS6
DIMM_DQS6
105
B14
DIMM_DQS7
DIMM_DQS7
114
C17
DIMM_DQS8
DIMM_DQS8
46
B6
DIMM_ODT_R1
DIMM_ODT1
77
AE23
DIMM_RASN_R
DIMM_RASN
192
AE20
DIMM_WEN_R
DIMM_WEN
73
AA17
VREF
1
1.8V
51
1.8V
53
Table 2–21. DDR2 SDRAM DIMM Pin-Outs (Part 4 of 8)
Note (1)
Cyclone II (U12)
Signal Name
(2)
DIMM (J8) Signal
Name
(2)
DIMM (J8) Pin
Number
Cyclone II (U12)
Pin Number
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)