Altera Cyclone II DSP Development Board User Manual
Page 56
2–48
Reference Manual
Altera Corporation
Cyclone II DSP Development Board
August 2006
Expansion Connectors
EVM_A15
U40.9
J25
EVM_A16
U40.8
C25
EVM_A17
U40.7
G26
EVM_A18
U40.6
C24
EVM_A19
U40.5
H25
EVM_A2
U40.26
E25
EVM_A20
U40.4
B25
EVM_A21
U40.3
F26
EVM_A3
U40.25
L24
EVM_A4
U40.24
E26
EVM_A5
U40.23
L25
EVM_A6
U40.20
E24
EVM_A7
U40.19
K26
EVM_A8
U40.18
E23
EVM_A9
U40.17
K25
EVM_ARDY
U40.76
W23
EVM_AREN
U40.73
P26
EVM_AWEN
U40.74
V23
EVM_BEN0
U40.30
F23
EVM_BEN1
U40.29
M23
EVM_BEN2
U40.28
F25
EVM_BEN3
U40.27
M24
EVM_CEN2
U40.78
J24
EVM_CEN3
U40.77
AE25
EVM_CLKOUT2
U34.78
P2
EVM_CLKR0
U34.27
G25
EVM_CLKX0
U34.21
F24
EVM_CNTL0
U34.64
M21
EVM_D0
U40.70
V22
EVM_D1
U40.69
AB25
EVM_D10
U40.58
L21
EVM_D11
U40.57
Y26
Table 2–25. TI-EVM Connector Pin-Outs (Part 2 of 4)
Schematic Signal
Name
TI-EVM Connector (U34, U40)
Pin Number
Cyclone II (U12) Pin
Number
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)