Altera Cyclone II DSP Development Board User Manual
Page 84

B–2
Reference Manual
Altera Corporation
Cyclone II DSP Development Board
August 2006
Introduction
EVM_A14
SRAM_A14
46
D23
EVM_A15
SRAM_A15
47
J25
EVM_A16
SRAM_A16
48
C25
EVM_A17
SRAM_A17
49
G26
EVM_A18
SRAM_A7
50
C24
EVM_A19
SRAM_A8
34
H25
EVM_A20
SRAM_A9
32
B25
EVM_A21
SRAM_A10
99
F26
EVM_BEn0
SRAM_BEn0
93
F23
EVM_BEn1
SRAM_BEn1
94
M23
EVM_BEn2
SRAM_BEn2
95
F25
EVM_BEn3
SRAM_BEn3
96
M24
EVM_AWEn
SRAM_BWEn
87
V23
EVM_CEn2
SRAM_CEn1
98
J24
EVM_CNTL0
EVM_ADVn
83
M21
EVM_D0
SRAM_D15
79
V22
EVM_D1
SRAM_D24
2
AB25
EVM_D2
SRAM_D14
78
M19
EVM_D3
SRAM_D25
3
AB26
EVM_D4
SRAM_D13
75
N20
EVM_D5
SRAM_D26
6
AA25
EVM_D6
SRAM_D12
74
M20
EVM_D7
SRAM_D27
7
AA26
EVM_D8
SRAM_D11
73
L19
EVM_D9
SRAM_D28
8
AA24
EVM_D10
SRAM_D10
72
L21
EVM_D11
SRAM_D29
9
Y26
EVM_D12
SRAM_D9
69
K19
EVM_D13
SRAM_D30
12
W24
EVM_D14
SRAM_D8
68
K21
EVM_D15
SRAM_D31
13
U22
EVM_D16
SRAM_D7
63
K22
Table B–1. Cyclone II to SSRAM Device Signal Changes (Part 2 of 3)
(1)
Cyclone II (U12) Signal
Name
SSRAM (U22) Signal
Name
SSRAM (U22) Pin
Cyclone II (U12) Pin
Name
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)