Altera Cyclone II DSP Development Board User Manual
Page 80
A–2
Reference Manual
Altera Corporation
Cyclone II DSP Development Board
August 2006
Introduction
DIMM_DQ13
Y14
Y14
No
DIMM_DQ14
Y15
AA13
Yes
DIMM_DQ15
AA15
AE12
Yes
DIMM_DQ16
AE9
AC11
Yes
DIMM_DQ17
AF9
AD10
Yes
DIMM_DQ18
AD10
AE10
Yes
DIMM_DQ19
AC11
AE9
Yes
DIMM_DQ20
AE10
AB12
Yes
DIMM_DQ21
AF10
AD11
Yes
DIMM_DQ22
AB12
AF10
Yes
DIMM_DQ23
AD11
AF9
Yes
DIMM_DQ24
AE6
AB10
Yes
DIMM_DQ25
AF6
AA10
Yes
DIMM_DQ26
AA9
AE6
Yes
DIMM_DQ27
AA10
AE7
Yes
DIMM_DQ28
AB10
Y11
Yes
DIMM_DQ29
AA11
AA11
No
DIMM_DQ30
Y11
AF6
Yes
DIMM_DQ31
AE7
AA9
Yes
DIMM_DQ32
F11
F11
No
DIMM_DQ33
C9
D8
Yes
DIMM_DQ34
D9
C8
Yes
DIMM_DQ35
G10
D9
Yes
DIMM_DQ36
F10
G10
Yes
DIMM_DQ37
C8
F10
Yes
DIMM_DQ38
D8
A7
Yes
DIMM_DQ39
A7
C9
Yes
DIMM_DQ40
F12
B10
Yes
DIMM_DQ41
D12
A10
Yes
DIMM_DQ42
E12
F12
Yes
DIMM_DQ43
G11
G11
No
DIMM_DQ44
A10
D10
Yes
Table A–1. Cyclone II EP2C70F672 DSP Development Board to DIMM Pin Changes (Part 2 of 4)
Signal Name
Original DDR2 Core Location
EP2C70F672 Board
Location
Different
(Yes/No)
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)