Altera Cyclone II DSP Development Board User Manual
Page 38
2–30
Reference Manual
Altera Corporation
Cyclone II DSP Development Board
August 2006
Memory Components
DIMM_DM0
DIMM_DM0
125
AC15
DIMM_DM1
DIMM_DM1
134
AA12
DIMM_DM2
DIMM_DM2
146
AC9
DIMM_DM3
DIMM_DM3
155
AD8
DIMM_DM4
DIMM_DM4
202
D6
DIMM_DM5
DIMM_DM5
211
B9
DIMM_DM6
DIMM_DM6
223
G12
DIMM_DM7
DIMM_DM7
232
C16
DIMM_DM8
DIMM_DM8
164
A4
DIMM_DQ0
DIMM_DQ0
3
AA16
DIMM_DQ1
DIMM_DQ1
4
AC17
DIMM_DQ2
DIMM_DQ2
9
AE17
DIMM_DQ3
DIMM_DQ3
10
AF17
DIMM_DQ4
DIMM_DQ4
122
Y16
DIMM_DQ5
DIMM_DQ5
123
AD17
DIMM_DQ6
DIMM_DQ6
128
AF18
DIMM_DQ7
DIMM_DQ7
129
AD16
DIMM_DQ8
DIMM_DQ8
12
Y15
DIMM_DQ9
DIMM_DQ9
13
AA15
DIMM_DQ10
DIMM_DQ10
21
AC14
DIMM_DQ11
DIMM_DQ11
22
AD12
DIMM_DQ12
DIMM_DQ12
131
Y13
DIMM_DQ13
DIMM_DQ13
132
Y14
DIMM_DQ14
DIMM_DQ14
140
AA13
DIMM_DQ15
DIMM_DQ15
141
AE12
DIMM_DQ16
DIMM_DQ16
24
AC11
DIMM_DQ17
DIMM_DQ17
25
AD10
DIMM_DQ18
DIMM_DQ18
30
AE10
DIMM_DQ19
DIMM_DQ19
31
AE9
DIMM_DQ20
DIMM_DQ20
143
AB12
DIMM_DQ21
DIMM_DQ21
144
AD11
DIMM_DQ22
DIMM_DQ22
149
AF10
Table 2–21. DDR2 SDRAM DIMM Pin-Outs (Part 2 of 8)
Note (1)
Cyclone II (U12)
Signal Name
(2)
DIMM (J8) Signal
Name
(2)
DIMM (J8) Pin
Number
Cyclone II (U12)
Pin Number
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)